In conventional CMOS RAMs, dc currents flow constantly through the devices, and the dc currents increase with the increase of memory capacity for one chip caused by the increase of integration density.
One method proposed to solve this problem is a so-called edge sense circuit system wherein clocks are not supplied from the outside but are generated internally to be used for its dynamic operation by detecting changes of address signals. Under this system which is also called as an internally synchronized circuit system, dc currents do not flow, and only the charging current flows in the dynamic operation, thereby reducing currents to a great extent.
To exemplify a conventional edge sense type CMOS RAM, reference will be particularly made to FIG. 1.
The reference numeral 1 designates terminals for an address input, and the reference numeral 2 designates an edge detector which detects the change of the input address signal. The reference numeral 3 designates a NOR gate to which the outputs of the edge detectors 2 are input. The reference numeral 4 designates a pre-charge signal generator which generates a pre-charge signal .phi.p. The reference numeral 5 designates a word line control circuit which controls the word line B so as to select a desired memory cell. The reference numeral 6 designates a memory cell, the reference numeral 7 designates a Y-address decoder, and the reference numeral 8 designates a sense amplifier for amplifying the output signal from the memory cell 6. The reference numeral 9 designates an output buffer for taking the output signal to the outside. The reference symbols A, B, C, and D designate a pre-charge signal (.phi.p) line, a word line (WL), a pair of bit lines (BL), and input/output (I/O) lines, respectively. The reference symbol E designates two output lines of the sense amplifier 8. The reference symbol Q.sub.1 designates a transistor for charging the bit lines C, and the reference symbol Q.sub.2 designates a switching transistor for connecting or disconnecting the bit lines C and the I/O lines D.
The device will be operated as follows:
When the input address signal 1 changes, the edge detector 2 detects the change, and outputs a one-shot pulse. The NOR gate 3 operates to transmit any pulse to the next stage which is generated by any one of the edge detectors 2. The pre-charge signal generator 4 generates a negative one-shot pulse when it receives the pulse from the NOR circuit 3.
When the pre-charge signal .phi.p on the line A becomes "L" level at time t.sub.1 in FIG. 2, the P-channel transistor Q.sub.1 turns on, and charges the bit lines C and the I/O lines D up to the "H" level. Then, the output lines E of the sense amplifier 8 are reset to "L" level. The pre-charge signal .phi.p recovers to "H" level at time t.sub.2 after the charging is completed.
Next, the word line control circuit 5 operates to make the word line B rise to the "H" level after the pre-charge signal .phi.p becomes "H" level. The memory cell 6 is driven by this rising of the word line B, and either one of a pair of bit lines C associated with a memory cell, 6 is discharged to become "L" level in accordance with the content of that memory cell 6. Then, the I/O lines D change in the same way as either one of the pair of the bit lines C to which the I/O lines D are connected through corresponding pair of transistors Q.sub.2 which are turned on by the output of the corresponding Y-address decoder 7.
At time t.sub.3 when the voltage of one of the I/O lines D decreases to some extent and a voltage difference arises between the pair of I/O lines D, one of the lines E rises up to the "H" level. Thereafter, data is output at the output terminal 10 through the output buffer 9. After time t.sub.3, the bit lines C and the I/O lines D continue to discharge being driven by the memory cell 6, and finally fall to ground level.
The flowing current Icc through the device throughout this operation is a charging current from only in the time t.sub.1 to t.sub.3, and no current flows after time t.sub.3 when the operation is completed. Accordingly, the average current in one cycle becomes very small. However, in this system, all the bit lines are charged at the same time, resulting in a sharp rising and falling in the current (Icc) waveform.
Under the conventional system described above, it is necessary to charge the bit lines up to the power supply voltage from the ground level, and this causes an increase of charging currents with the increased number of bit lines caused by increasing the memory capacity for one chip. This results in not only an increased power consumption but also a sharp rising and falling in the current waveform, which gives rise to noise inside and outside of the chip, possibly leading to a malfunction of the device.